SH7243 datasheet(126/1726 Pages) RENESAS

126 / 1726 page

Section 5 Exception Handling

Rev. 1.00 Jun. 26, 2008 Page 96 of 1692

REJ09B0393-0100

Type

Exception Handling

Priority

Interrupt

On-chip peripheral modules

Port output enable 2 (POE2): OEI1 and

OEI2 interrupts

Multi-function timer pulse unit 2S (MTU2S)

Port output enable 2 (POE2): OEI3

interrupt

USB function module (USB) USI0/USI1

2C bus interface 3 (IIC3)

Synchronous serial communication unit

(SSU)

Serial communication interface (SCI)

Serial communication interface with FIFO

(SCIF)

Trap instruction (TRAPA instruction)

General illegal instructions (undefined code)

Instruction

Slot illegal instructions (undefined code placed directly after a delayed

branch instruction*

1, instructions that rewrite the PC*2, 32-bit

instructions*

3, RESBANK instruction, DIVS instruction, and DIVU

instruction)

High

Low

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF.

2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.

3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,

BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,

MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.

SH7243 Datasheet(PDF) 126 Page - Renesas Technology Corp