SH7243 datasheet(112/1726 Pages) RENESAS

Part #	SH7243

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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112 / 1726 page

Section 4 Clock Pulse Generator (CPG)

Rev. 1.00 Jun. 26, 2008 Page 82 of 1692

REJ09B0393-0100

Bit

Bit Name

Initial

Value

R/W

Description

15 to 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

10 to 8

STC[2:0]

011

R/W

Bus Clock (B

φ) Frequency Division Ratio

These bits specify the frequency division ratio of the

bus clock.

000:

× 1

001:

× 1/2

010: Setting prohibited

011:

× 1/4

100: Setting prohibited

101:

× 1/8

Others: Setting prohibited



Reserved

This bit is always read as 0. The write value should

always be 0.

6 to 4

IFC[2:0]

011

R/W

Internal Clock (I

φ) Frequency Division Ratio

These bits specify the frequency division ratio of the

internal clock.

000:

× 1

001:

× 1/2

010: Setting prohibited

011:

× 1/4

100: Setting prohibited

101:

× 1/8

Others: Setting prohibited



Reserved

This bit is always read as 0. The write value should

always be 0.

SH7243 Datasheet(PDF) 112 Page - Renesas Technology Corp

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