SH7243 datasheet(135/1726 Pages) RENESAS

135 / 1726 page

Section 5 Exception Handling

Rev. 1.00 Jun. 26, 2008 Page 105 of 1692

REJ09B0393-0100

5.3

Address Errors

5.3.1

Address Error Sources

Address errors occur when instructions are fetched or data read or written, as shown in table 5.6.

Table 5.6

Bus Cycles and Address Errors

Bus Cycle

Type

Bus

Master

Bus Cycle Description

Address Errors

Instruction fetched from even address

None (normal)

Instruction fetched from odd address

Address error occurs

Instruction fetched from other than on-chip

peripheral module space* or H'F0000000 to

H'F5FFFFFF in on-chip RAM space*

None (normal)

Instruction fetched from on-chip peripheral

module space* or H'F0000000 to

H'F5FFFFFF in on-chip RAM space*

Address error occurs

Instruction

fetch

CPU

Instruction fetched from external memory

space in single-chip mode

Address error occurs

Word data accessed from even address

None (normal)

Word data accessed from odd address

Address error occurs

Longword data accessed from a longword

boundary

None (normal)

Longword data accessed from other than a

long-word boundary

Address error occurs

Byte or word data accessed in on-chip

peripheral module space*

None (normal)

Longword data accessed in 16-bit on-chip

peripheral module space*

None (normal)

Longword data accessed in 8-bit on-chip

peripheral module space*

None (normal)

Data

read/write

CPU,

DMAC, or

DTC

External memory space accessed when in

single chip mode

Address error occurs

Note:

See section 9, Bus State Controller (BSC), for details of the on-chip peripheral module

space and on-chip RAM space.

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