SH7243 datasheet(136/1726 Pages) RENESAS

136 / 1726 page

Section 5 Exception Handling

Rev. 1.00 Jun. 26, 2008 Page 106 of 1692

REJ09B0393-0100

5.3.2

Address Error Exception Handling

When an address error occurs, the bus cycle in which the address error occurred ends*. When the

executing instruction then finishes, address error exception handling starts. The CPU operates as

follows:

1. The exception service routine start address which corresponds to the address error that

occurred is fetched from the exception handling vector table.

2. The status register (SR) is saved to the stack.

3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the last executed instruction.

4. After jumping to the address fetched from the exception handling vector table, program

execution starts. The jump that occurs is not a delayed branch.

Note: * In the case of an address error caused by instruction fetching when data is read or

written, if the bus cycle on which the address error occurred is not completed by the

end of the operations described above operation 3, the CPU will recommence address

error exception processing until the end of that bus cycle.

SH7243 Datasheet(PDF) 136 Page - Renesas Technology Corp