Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

SH7243 Datasheet(PDF) 207 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 207 Page - Renesas Technology Corp

Back Button SH7243 Datasheet HTML 203Page - Renesas Technology Corp SH7243 Datasheet HTML 204Page - Renesas Technology Corp SH7243 Datasheet HTML 205Page - Renesas Technology Corp SH7243 Datasheet HTML 206Page - Renesas Technology Corp SH7243 Datasheet HTML 207Page - Renesas Technology Corp SH7243 Datasheet HTML 208Page - Renesas Technology Corp SH7243 Datasheet HTML 209Page - Renesas Technology Corp SH7243 Datasheet HTML 210Page - Renesas Technology Corp SH7243 Datasheet HTML 211Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 207 / 1726 page
background image
Section 7 User Break Controller (UBC)
Rev. 1.00 Jun. 26, 2008 Page 177 of 1692
REJ09B0393-0100
7.3.7
Break Address Register_2 (BAR_2)
BAR_2 is a 32-bit readable/writable register. BAR_2 specifies the address used as a break
condition in channel 2. The control bits CD2_1 and CD2_0 in the break bus cycle register_2
(BBR_2) select one of the three address buses for a break condition of channel 2. BAR_2 is
initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or
in software standby mode or sleep mode.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0000000000000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000000000000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
BA2_31 BA2_30 BA2_29 BA2_28 BA2_27 BA2_26 BA2_25 BA2_24 BA2_23 BA2_22 BA2_21 BA2_20 BA2_19 BA2_18 BA2_17 BA2_16
BA2_15 BA2_14 BA2_13 BA2_12 BA2_11 BA2_10 BA2_9 BA2_8 BA2_7 BA2_6 BA2_5 BA2_4 BA2_3 BA2_2 BA2_1 BA2_0
Bit
Bit Name
Initial
Value
R/W
Description
31 to 0
BA2_31 to
BA2_0
All 0
R/W
Break Address 2
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions of channel 2.
When the C bus and instruction fetch cycle are
selected by BBR_2, specify an FAB address in bits
BA2_31 to BA2_0.
When the C bus and data access cycle are selected by
BBR_2, specify an MAB address in bits BA2_31 to
BA0_2.
Note:
When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_2 to 0.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com