SH7243 datasheet(209/1726 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 1.00 Jun. 26, 2008 Page 179 of 1692

REJ09B0393-0100

7.3.9

Break Bus Cycle Register_2 (BBR_2)

BBR_2 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user

break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C

bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size

as the break conditions of channel 2. BBR_2 is initialized to H'0000 by a power-on reset, but

retains its previous value by a manual reset or in software standby mode or sleep mode.

0000000000000000

R/W

Bit:

Initial value:

R/W:

UBID2

CP2[2:0]

CD2[1:0]

ID2[1:0]

RW2[1:0]

SZ2[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

15, 14



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

UBID2

R/W

User Break Interrupt Disable 2

Disables or enables user break interrupt requests

when a channel-2 break condition is satisfied.

0: User break interrupt requests enabled

1: User break interrupt requests disabled

12, 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

10 to 8

CP2[2:0]

000

R/W

I-Bus Bus Master Select 2

Select the bus master when the bus cycle of the

channel-2 break condition is the I bus cycle. However,

when the C bus cycle is selected, this bit is invalidated

(only the CPU cycle).

xx1: CPU cycle is included in break conditions

x1x: DMAC cycle is included in break conditions

1xx: DTC cycle is included in break conditions

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