SH7243 datasheet(211/1726 Pages) RENESAS

211 / 1726 page

Section 7 User Break Controller (UBC)

Rev. 1.00 Jun. 26, 2008 Page 181 of 1692

REJ09B0393-0100

7.3.10

Break Address Register_3 (BAR_3)

BAR_3 is a 32-bit readable/writable register. BAR_3 specifies the address used as a break

condition in channel 3. The control bits CD3_1 and CD3_0 in the break bus cycle register_3

(BBR_3) select one of the three address buses for a break condition of channel 3. BAR_3 is

initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or

in software standby mode or sleep mode.

0000000000000000

R/W

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

BA3_31 BA3_30 BA3_29 BA3_28 BA3_27 BA3_26 BA3_25 BA3_24 BA3_23 BA3_22 BA3_21 BA3_20 BA3_19 BA3_18 BA3_17 BA3_16

BA3_15 BA3_14 BA3_13 BA3_12 BA3_11 BA3_10 BA3_9 BA3_8 BA3_7 BA3_6 BA3_5 BA3_4 BA3_3 BA3_2 BA3_1 BA3_0

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BA3_31 to

BA3_0

All 0

R/W

Break Address 3

Store an address on the CPU address bus (FAB or

MAB) or IAB specifying break conditions of channel 3.

When the C bus and instruction fetch cycle are

selected by BBR_3, specify an FAB address in bits

BA3_31 to BA3_0.

When the C bus and data access cycle are selected by

BBR_3, specify an MAB address in bits BA3_31 to

BA3_0.

Note:

When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_3 to 0.

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