SH7243 datasheet(224/1726 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 1.00 Jun. 26, 2008 Page 194 of 1692

REJ09B0393-0100

(Example 1-3)

• Register specifications

BBR_0 = H'0054, BAR_0 = H'00008404, BAMR_0 = H'00000FFF, BBR_1 = H'0054,

BAR_1 = H'00008010, BAMR_1 = H'00000006, BRCR = H'00000020

Address:

H'00008404, Address mask: H'00000FFF

Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not

included in the condition)

Address:

H'00008010, Address mask: H'00000006

Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is

executed or before an instruction with addresses H'00008010 to H'00008016 are executed.

(2)

Break Condition Specified for C Bus Data Access Cycle

(Example 2-1)

• Register specifications

BBR_0 = H'0064, BAR_0 = H'00123456, BAMR_0 = H'00000000,

BBR_1 = H'006A, BAR_1 = H'000ABCDE, BAMR_1 = H'000000FF, BRCR = H'00000000

Address:

H'00123456, Address mask: H'00000000

Bus cycle: C bus/data access/read (operand size is not included in the condition)

Address:

H'000ABCDE, Address mask: H'000000FF

Bus cycle: C bus/data access/write/word

On channel 0, a user break occurs with longword read from address H'00123456, word read

from address H'00123456, or byte read from address H'00123456. On channel 1, a user break

occurs when word is written in addresses H'000ABC00 to H'000ABCFE.

SH7243 Datasheet(PDF) 224 Page - Renesas Technology Corp