SH7243 datasheet(228/1726 Pages) RENESAS

Part #	SH7243

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 198 of 1692

REJ09B0393-0100

Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to

the data area*.

Note:

When the transfer information is stored in the on-chip RAM, the RAME bit in RAMCR

must be set to 1.

Bus interface

Interrupt source

clear request

DTC

CPU interrupt

request

control

CPU/DTC

request

determination

Interrupt

control

Interrupt

request

On-chip

memory

MRA

MRB

SAR

DAR

CRA

CRB

On-chip

peripheral

module

External

memory

External device

(memory mapped)

Bus state

controller

MRA, MRB:

SAR:

DAR:

CRA, CRB:

DTCERA to DTCERE:

DTCCR:

DTCVBR:

DTC mode registers A, B

DTC source address register

DTC destination address register

DTC transfer count registers A, B

DTC enable registers A to E

DTC control register

DTC vector base register

[Legend]

DTCERA to

DTCERE

DTCCR

DTCVBR

Activation

control

INTC

Figure 8.1 Block Diagram of DTC

SH7243 Datasheet(PDF) 228 Page - Renesas Technology Corp

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