SH7243 datasheet(229/1726 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 199 of 1692

REJ09B0393-0100

8.2

DTC has the following registers. For details on the addresses of these registers and the states of

these registers in each processing state, see section 30, List of Registers.

These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the

CPU. The contents of these registers are stored in the data area as transfer information. When a

DTC activation request occurs, the DTC reads a start address of transfer information that is stored

in the data area according to the vector address, reads the transfer information, and transfers data.

After the data transfer is complete, it writes a set of updated transfer information back to the data

area.

On the other hand, DTCERA to DTCERE, DTCCR, and DTCVBR can be directly accessed by the

CPU.

Table 8.1

Abbrevia-

tion

R/W

Initial Value

Address

Access Size

DTC enable register A

DTCERA

R/W

H'0000

H'FFFE6000

8, 16

DTC enable register B

DTCERB

R/W

H'0000

H'FFFE6002

8, 16

DTC enable register C

DTCERC

R/W

H'0000

H'FFFE6004

8, 16

DTC enable register D

DTCERD

R/W

H'0000

H'FFFE6006

8, 16

DTC enable register E

DTCERE

R/W

H'0000

H'FFFE6008

8, 16

DTC control register

DTCCR

R/W

H'00

H'FFFE6010

DTC vector base register

DTCVBR

R/W

H'00000000

H'FFFE6014

8, 16, 32

Bus function extending register BSCEHR

R/W

H'0000

H'FFFE3C1A

8, 16

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