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SH7243 Datasheet(PDF) 233 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 233 Page - Renesas Technology Corp |
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233 / 1726 page  Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 203 of 1692 REJ09B0393-0100 8.2.3 DTC Source Address Register (SAR) SAR is a 32-bit register that designates the source address of data to be transferred by the DTC. SAR cannot be accessed directly from the CPU. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 : Undefined * **************** ---------------- **************** ---------------- 8.2.4 DTC Destination Address Register (DAR) DAR is a 32-bit register that designates the destination address of data to be transferred by the DTC. DAR cannot be accessed directly from the CPU. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 : Undefined * **************** ---------------- **************** ---------------- |
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