SH7243 datasheet(237/1726 Pages) RENESAS

237 / 1726 page

Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 207 of 1692

REJ09B0393-0100

8.2.8

DTC Control Register (DTCCR)

DTCCR specifies transfer information read skip.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

R/(W)*

Note:

Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

RRS

RCHNE

ERR

Bit

Bit Name

Initial

Value

R/W

Description

7 to 5



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

RRS

R/W

DTC Transfer Information Read Skip Enable

Controls the vector address read and transfer information

read. A DTC vector number is always compared with the

vector number for the previous activation. If the vector

numbers match and this bit is set to 1, the DTC data

transfer is started without reading a vector address and

transfer information. If the previous DTC activation is a

chain transfer, the vector address read and transfer

information read are always performed.

0: Transfer read skip is not performed.

1: Transfer read skip is performed when the vector

numbers match.

RCHNE

R/W

Chain Transfer Enable After DTC Repeat Transfer

Enables/disables the chain transfer while transfer counter

(CRAL) is 0 in repeat transfer mode.

In repeat transfer mode, the CRAH value is written to

CRAL when CRAL is 0. Accordingly, chain transfer may

not occur when CRAL is 0. If this bit is set to 1, the chain

transfer is enabled when CRAH is written to CRAL.

0: Disables the chain transfer after repeat transfer

1: Enables the chain transfer after repeat transfer

2, 1



All 0

Reserved

These are read-only bits and cannot be modified.

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