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SH7243 Datasheet(PDF) 239 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 239 Page - Renesas Technology Corp

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Section 8 Data Transfer Controller (DTC)
Rev. 1.00 Jun. 26, 2008 Page 209 of 1692
REJ09B0393-0100
8.2.9
DTC Vector Base Register (DTCVBR)
DTCVBR is a 32-bit register that specifies the base address for vector table address calculation.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987654321
0
0000000000000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000000000000000
R/W
R/W
R/W
R/W
RRRRRRRRRRRR
------------
Bit
Bit Name
Initial
Value
R/W
Description
31 to 12
All 0
R/W
11 to 0
All 0
R
Bits 11 to 0 are always read as 0. The write value should
always be 0.
8.2.10
Bus Function Extending Register (BSCEHR)
BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC and other
functions. This register should be used to give priority to the DTC transfer or reduce the number
of cycles in which the DTC is active. For more details, see section 9.4.8, Bus Function Extending
Register (BSCEHR).



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