SH7243 datasheet(234/1726 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 204 of 1692

REJ09B0393-0100

8.2.5

DTC Transfer Count Register A (CRA)

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is

decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the

activation source is cleared and then an interrupt is requested to the CPU when the count reaches

H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536

when CRA = H'0000.

In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower

eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit

transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the

contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when

CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL =

H'00.

In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower

eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size

counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte

(word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the

count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01,

255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or

longwords) when CRAH = CRAL =H'00.

CRA cannot be accessed directly from the CPU.

Bit:

Initial value:

R/W:

: Undefined

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