SH7243 datasheet(230/1726 Pages) RENESAS

230 / 1726 page

Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 200 of 1692

REJ09B0393-0100

8.2.1

DTC Mode Register A (MRA)

MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU.

Bit:

Initial value:

R/W:

7654321

********

--------

MD[1:0]

Sz[1:0]

SM[1:0]

: Undefined

Bit

Bit Name

Initial

Value

R/W

Description

7, 6

MD[1:0]

Undefined



DTC Mode 1 and 0

Specify DTC transfer mode.

00: Normal mode

01: Repeat mode

10: Block transfer mode

11: Setting prohibited

5, 4

Sz[1:0]

Undefined



DTC Data Transfer Size 1 and 0

Specify the size of data to be transferred.

00: Byte-size transfer

01: Word-size transfer

10: Longword-size transfer

11: Setting prohibited

3, 2

SM[1:0]

Undefined



Source Address Mode 1 and 0

Specify an SAR operation after a data transfer.

0x: SAR is fixed

(SAR write-back is skipped)

10: SAR is incremented after a transfer

(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and

Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)

11: SAR is decremented after a transfer

(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and

Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)

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