SH7243 datasheet(232/1726 Pages) RENESAS

Part #	SH7243

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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232 / 1726 page

Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 202 of 1692

REJ09B0393-0100

Bit

Bit Name

Initial

Value

R/W

Description

DTS

Undefined



DTC Transfer Mode Select

Specifies either the source or destination as repeat or

block area during repeat or block transfer mode.

0: Specifies the destination as repeat or block area

1: Specifies the source as repeat or block area

3, 2

DM[1:0]

Undefined



Destination Address Mode 1 and 0

Specify a DAR operation after a data transfer.

0x: DAR is fixed

(DAR write-back is skipped)

10: DAR is incremented after a transfer

(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and

Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)

11: SAR is decremented after a transfer

(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and

Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)

1, 0



Undefined



Reserved

The write value should always be 0.

[Legend]

Don't care

SH7243 Datasheet(PDF) 232 Page - Renesas Technology Corp