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SH7243 Datasheet(PDF) 225 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 225 Page - Renesas Technology Corp |
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225 / 1726 page  Section 7 User Break Controller (UBC) Rev. 1.00 Jun. 26, 2008 Page 195 of 1692 REJ09B0393-0100 (3) Break Condition Specified for I Bus Data Access Cycle (Example 3-1) • Register specifications BBR_0 = H'0094, BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_1 = H'12A9, BAR_1 = H'00055555, BAMR_1 = H'00000000, BRCR = H'00000000 <Channel 0> Address: H'00314156, Address mask: H'00000000 Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition) <Channel 1> Address: H'00055555, Address mask: H'00000000 Bus cycle: I bus/data access/write/byte On channel 0, the setting of I bus/instruction fetch is ignored. On channel 1, a user break occurs when the DMAC writes byte data in address H'00055555 on the I bus (write by the CPU does not generate a user break). |
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