SH7243 datasheet(252/1726 Pages) RENESAS

252 / 1726 page

Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 222 of 1692

REJ09B0393-0100

8.5.2

Transfer Information Write-Back Skip Function

By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer

information will not be written back. Table 8.5 shows the transfer information write-back skip

condition and write-back skipped registers. Note that the CRA and CRB are always written back.

The write-back of the MRA and MRB are always skipped.

Table 8.5

Transfer Information Write-Back Skip Condition and Write-Back Skipped

Registers

SM1

DM1

SAR

DAR

Skipped

Written back

Skipped

Written back

8.5.3

Normal Transfer Mode

In normal transfer mode, data are transferred in one byte, one word, or one longword units in

response to a single activation request. From 1 to 65,536 transfers can be specified. The transfer

source and destination addresses can be specified as incremented, decremented, or fixed. When

the specified number of transfers ends, an interrupt can be requested to the CPU.

Table 8.6 lists the register function in normal transfer mode. Figure 8.6 shows the memory map in

normal transfer mode.

Table 8.6

Function

Written Back Value

SAR

Source address

Incremented/decremented/fixed*

DAR

Destination address

Incremented/decremented/fixed*

CRA

Transfer count A

CRA

− 1

CRB

Transfer count B

Not updated

Note:

Transfer information write-back is skipped.

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