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SH7243 Datasheet(PDF) 255 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 255 Page - Renesas Technology Corp

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Section 8 Data Transfer Controller (DTC)
Rev. 1.00 Jun. 26, 2008 Page 225 of 1692
REJ09B0393-0100
8.5.5
Block Transfer Mode
In block transfer mode, data are transferred in block units in response to a single activation
request. Either the transfer source or the transfer destination is designated as a block area by the
DTS bit in MRB.
The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When transfer of one
block of data ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or
DAR when DTS = 0) for the area specified as the block area are initialized. The other address
register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be
specified. When the specified number of transfers ends, an interrupt is requested to the CPU.
Table 8.8 lists the register function in block transfer mode. Figure 8.8 shows the memory map in
block transfer mode.
Table 8.8
Register Function in Block Transfer Mode
Register Function
Written Back Value
SAR
Source address
DTS = 0: Incremented/decremented/fixed*
DTS = 1: SAR initial value
DAR
Destination address
DTS = 0: DAR initial value
DTS = 1: Incremented/decremented/fixed*
CRAH
Block size storage
CRAH
CRAL
Block size counter
CRAH
CRB
Block transfer counter
CRB
− 1
Note:
*
Transfer information write-back is skipped.



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