SH7243 datasheet(258/1726 Pages) RENESAS

258 / 1726 page

Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 228 of 1692

REJ09B0393-0100

8.5.7

Operation Timing

Figures 8.10 to 8.15 show the DTC operation timings.

Internal address

Vector read

Transfer information

read

Data

transfer

Transfer information

write

Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.

DTC activation

request

DTC request

Clock (B

φ)

Figure 8.10 Example of DTC Operation Timing:

Normal Transfer Mode or Repeat Transfer Mode

(Activated by On-Chip Peripheral Module; I

φ : Bφ : Pφ = 1 : 1/2 : 1/2;

Data Transferred from On-Chip Peripheral Module to On-Chip RAM;

Transfer Information is Written in 3 Cycles)

Internal address

Vector read

Transfer information

read

Data

transfer

Transfer information

write

Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.

DTC activation

request

DTC request

Clock (B

φ)

Figure 8.11 Example of DTC Operation Timing: Block Transfer Mode with Block Size = 2

(Activated by On-Chip Peripheral Module; I

φ : Bφ : Pφ = 1 : 1/2 : 1/2;

Data Transferred from On-Chip Peripheral Module to On-Chip RAM;

Transfer Information is Written in 3 Cycles)

SH7243 Datasheet(PDF) 258 Page - Renesas Technology Corp

SH7243 Datasheet(HTML) 258 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL