SH7243 datasheet(262/1726 Pages) RENESAS

262 / 1726 page

Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 232 of 1692

REJ09B0393-0100

Table 8.10

Number of Cycles Required for Each Execution State

Object to be Accessed

On-Chip

RAM*

On-Chip

ROM*

On-Chip I/O Registers

External Device*

Bus width

32 bits

8 bits*

16 bits

8 bits

16 bits

32 bits

Access cycles

φ to 3Bφ*1

φ to 4Iφ +

φ*2

Vector read S

φ to 3Bφ*1

φ to 4Iφ +

φ*2



Transfer information read

φ to 3Bφ*1



Exe-

cution

status

Transfer information write

φ to 3Bφ*1



φ*6

Byte data read S

φ to 3Bφ*1



φ + 2Pφ*3 1Bφ + 2Pφ*3 3Bφ

Word data read S

φ to 3Bφ*1



φ + 2Pφ*3 5Bφ

Longword data read S

φ to 3Bφ*1



φ + 2Pφ*3 9Bφ

Byte data write S

φ to 3Bφ*1



φ + 2Pφ*3 1Bφ + 2Pφ*3 2Bφ*6

φ*6

Word data write S

φ to 3Bφ*1



φ + 2Pφ*3 2Bφ*6

φ*6

Longword data write S

φ to 3Bφ*1



φ + 2Pφ*3 2Bφ*6

φ*6

Internal operation S

Notes: 1. Values for on-chip RAM. Number of cycles varies depending on the ratio of I

φ:Bφ.

Read

Write

φ:Bφ = 1:1

φ:Bφ = 1:1/2

φ:Bφ = 1:1/4

φ:Bφ = 1:1/8

2. Values for on-chip ROM. Number of cycles varies depending on the ratio of I

φ:Bφ.

Read

Write

φ:Bφ = 1:1

φ + 3Bφ

φ:Bφ = 1:1/2

φ + 3Bφ

φ:Bφ = 1:1/4

φ + 3Bφ

φ:Bφ = 1:1/8

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