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SH7243 Datasheet(PDF) 266 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 266 Page - Renesas Technology Corp

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Section 8 Data Transfer Controller (DTC)
Rev. 1.00 Jun. 26, 2008 Page 236 of 1692
REJ09B0393-0100
8.5.10
DTC Activation Priority Order
If multiple DTC activation requests are generated while the DTC is inactive, whether to start the
DTC transfer from the first activation request or according to the DTC activation priority can be
selected through the DTPR bit setting in the bus function extending register (BSCEHR). If
multiple activation requests are generated while the DTC is active, transfer is performed according
to the DTC activation priority. Figure 8.17 shows an example of DTC activation according to the
priority.
Transfer is started for the first activation request
Transfer is performed according to the priority
Transfer is performed according to the priority
Other than DTC
DTC
(request 3)
DTC
(request 1)
DTC
(request 2)
Internal bus
DTC activation request 1
(High priority)
DTC activation request 2
(Medium priority)
DTC activation request 3
(Low priority)
DTC activation request 1
(High priority)
DTC activation request 2
(Medium priority)
DTC activation request 3
(Low priority)
Priority
determination
Transfer is started according to the priority
Other than DTC
DTC
(request 1)
DTC
(request 2)
DTC
(request 3)
Internal bus
Priority
determination
Priority
determination
(1) DTPR = 0
(2) DTPR = 1
DTC is inactive
DTC is inactive
DTC is active
DTC is active
Figure 8.17 Example of DTC Activation According to Priority



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