SH7243 datasheet(265/1726 Pages) RENESAS

Part #	SH7243

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 235 of 1692

REJ09B0393-0100

Note: DTC request signal indicates the state of internal bus request after the DTC activation source is determined.

Clock (B

φ)

Vector

read

DTC request

DTC activation

request 1

DTC activation

request 2

Vector

read

Transfer information

read

Data

transfer

Transfer

information

write

Bus release timing

(setting 3)

Bus release timing

(setting 1)

Bus release timing

(setting 2)

: Indicates bus mastership release timing.

Internal address

: Bus mastership is only released for the external access request from the CPU.

Transfer information

read

Data

transfer

Transfer

information

write

Figure 8.16 Example of DTC Operation Timing:

Conflict of Two Activation Requests in Normal Transfer Mode

(Activated by On-Chip Peripheral Module; I

φ : Bφ : Pφ = 1 : 1/2 : 1/2;

Data Transferred from On-Chip Peripheral Module to On-Chip RAM;

Transfer Information is Written in 3 Cycles)

SH7243 Datasheet(PDF) 265 Page - Renesas Technology Corp

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