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SH7243 Datasheet(PDF) 253 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 253 Page - Renesas Technology Corp |
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253 / 1726 page  Section 8 Data Transfer Controller (DTC) Rev. 1.00 Jun. 26, 2008 Page 223 of 1692 REJ09B0393-0100 SAR Transfer source data area DAR Transfer Transfer destination data area Figure 8.6 Memory Map in Normal Transfer Mode 8.5.4 Repeat Transfer Mode In repeat transfer mode, data are transferred in one byte, one word, or one longword units in response to a single activation request. By the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to 256 transfers can be specified. When the specified number of transfers ends, the transfer counter and address register specified as the repeat area is restored to the initial state, and transfer is repeated. The other address register is then incremented, decremented, or left fixed. In repeat transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU interrupt cannot be requested when DISEL = 0. Table 8.7 lists the register function in repeat transfer mode. Figure 8.7 shows the memory map in repeat transfer mode. |
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