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SH7243 Datasheet(PDF) 271 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 271 Page - Renesas Technology Corp

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Section 8 Data Transfer Controller (DTC)
Rev. 1.00 Jun. 26, 2008 Page 241 of 1692
REJ09B0393-0100
8.8
Interrupt Sources
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or on completion of a single data transfer or a single block data transfer with the DISEL
bit set to 1. In the case of interrupt activation, the interrupt set as the activation source is
generated. These interrupts to the CPU are subject to CPU mask level and priority level control in
the interrupt controller. For details, refer to section 6.9, Data Transfer with Interrupt Request
Signals.



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