SH7243 datasheet(272/1726 Pages) RENESAS

272 / 1726 page

Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 242 of 1692

REJ09B0393-0100

8.9

Usage Notes

8.9.1

Module Standby Mode Setting

Operation of the DTC can be disabled or enabled using the standby control register. The initial

setting is for operation of the DTC to be disabled. DTC operation is disabled in module standby

mode but register access is available. However, do not place the DTC in module standby mode

while it is active. Before entering software standby mode or module standby mode, all DTCER

registers must be cleared. For details, refer to section 28, Power-Down Modes.

8.9.2

On-Chip RAM

Transfer information can be located in on-chip RAM. In this case, the RAME bit in RAMCR must

not be cleared to 0.

8.9.3

DTCE Bit Setting

To set a DTCE bit, disable the corresponding interrupt, read 0 from the bit, and then write 1 to it.

While DTC transfer is in progress, do not modify the DTCE bits.

8.9.4

Chain Transfer

When chain transfer is used, clearing of the activation source or DTCER is performed when the

last of the chain of data transfers is executed. SCI, SSU, RCAN-ET, SCIF, IIC3, and A/D

converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes

to the relevant register.

Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the

relevant register is not included in the last chained data transfer, the interrupt or activation source

will be retained.

8.9.5

Transfer Information Start Address, Source Address, and Destination Address

The transfer information start address to be specified in the vector table should be address 4n.

Transfer information should be placed in on-chip RAM or external memory space.

SH7243 Datasheet(PDF) 272 Page - Renesas Technology Corp