 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SH7243 Datasheet(PDF) 276 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7243 Datasheet(HTML) 276 Page - Renesas Technology Corp |
|
|
276 / 1726 page  Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 246 of 1692 REJ09B0393-0100 6. SRAM interface with byte selection Can connect directly to a SRAM with byte selection. 7. Burst ROM interface (clock synchronous) Can connect directly to a ROM of the clock-synchronous type. 8. Bus arbitration Shares all of the resources with other CPU and outputs the bus enable after receiving the bus request from external devices. 9. Refresh function Supports the auto-refresh and self-refresh functions. Specifies the refresh interval using the refresh counter and clock selection. Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8). 10. Usage as interval timer for refresh counter Generates an interrupt request at compare match. Figure 9.1 shows a block diagram of the BSC. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
