SH7243 datasheet(279/1726 Pages) RENESAS

Part #	SH7243

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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279 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 249 of 1692

REJ09B0393-0100

Name

I/O

Function

WRL/DQMLL

Output

Indicates that D7 to D0 are being written to.

Connected to the byte select signal when a SRAM with byte selection

is connected.

Functions as the select signals for D7 to D0 when SDRAM is

connected.

RASL, RASU

Output

Connected to

RAS pin when SDRAM is connected (RASU is available

only in the SH7286).

CASL, CASU

Output

Connected to

CAS pin when SDRAM is connected (CASU is available

only in the SH7286).

CKE

Output

Connected to CKE pin when SDRAM is connected.

WAIT

Input

External wait input

BREQ

Input

Bus request input

BACK

Output

Bus enable output

REFOUT

Output

Refresh request output in bus-released state

MD0

Input

Selects bus width of area 0.

8 or 16 bits: SH7285 and SH7243

16 or 32 bits: SH7286

It also selects the on-chip ROM enabled or disabled mode and external

bus access enabled or disabled mode.

SH7243 Datasheet(PDF) 279 Page - Renesas Technology Corp

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