SH7243 datasheet(282/1726 Pages) RENESAS

282 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 252 of 1692

REJ09B0393-0100

Table 9.3

Address Map in On-Chip ROM-Disabled Mode

Address

Space

Memory to be Connected

Size

H'0000 0000 to H'03FF FFFF

CS0

Normal space, SRAM with byte selection,

burst ROM (asynchronous or synchronous)

64 Mbytes

H'0400 0000 to H'07FF FFFF

CS1

Normal space, SRAM with byte selection

64 Mbytes

H'0800 0000 to H'0BFF FFFF

CS2

Normal space, SRAM with byte selection,

SDRAM

64 Mbytes

H'0C00 0000 to H'0FFF FFFF

CS3

Normal space, SRAM with byte selection,

SDRAM

64 Mbytes

H'1000 0000 to H'13FF FFFF

CS4

Normal space, SRAM with byte selection,

burst ROM (asynchronous)

64 Mbytes

H'1400 0000 to H'17FF FFFF

CS5

Normal space, SRAM with byte selection,

MPX-I/O

64 Mbytes

H'1800 0000 to H'1BFF FFFF

CS6

Normal space, SRAM with byte selection

64 Mbytes

H'1C00 0000 to H'1FFF FFFF

CS7

Normal space, SRAM with byte selection

64 Mbytes

H'2000 0000 to H'FFF7 FFFF

Other

Reserved area



H'FFF8 0000 to H'FFFB FFFF

Other

On-chip RAM, reserved area*



H'FFFC 0000 to H'FFFF FFFF

Other

On-chip peripheral modules, reserved area*



Note:

For the on-chip RAM space, access the addresses shown in section 27, On-Chip RAM.

For the on-chip I/O register space, access the addresses shown in section 30, List of

Registers. Do not access addresses which are not described in these sections.

Otherwise, the correct operation cannot be guaranteed.

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