SH7243 datasheet(286/1726 Pages) RENESAS

286 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 256 of 1692

REJ09B0393-0100

9.4.1

Common Control Register (CMNCR)

CMNCR is a 32-bit register that controls the common items for each area. This register is

initialized to H'00001010 by a power-on reset and retains the value by a manual reset and in

software standby mode.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0001000000010000

R/W

----------------

----

BLOCK

DPRTY[1:0]

DMAIW[2:0]

DMA

IWA

HIZ

CKIO

HIZ

MEM

HIZ

CNT

Bit

Bit Name

Initial

Value

R/W

Description

31 to 13



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.



Reserved

This bit is always read as 1. The write value should

always be 1.

BLOCK

R/W

Bus Lock

Specifies whether or not the

BREQ signal is received.

0: Receives

BREQ.

1: Does not receive

BREQ.

10, 9

DPRTY[1:0]

R/W

DMA Burst Transfer Priority

Specify the priority for a refresh request/bus

mastership request during DMA burst transfer.

00: Accepts a refresh request and bus mastership

request during DMA burst transfer.

01: Accepts a refresh request but does not accept a

bus mastership request during DMA burst transfer.

10: Accepts neither a refresh request nor a bus

mastership request during DMA burst transfer.

11: Reserved (setting prohibited)

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