SH7243 datasheet(287/1726 Pages) RENESAS

287 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 257 of 1692

REJ09B0393-0100

Bit

Bit Name

Initial

Value

R/W

Description

8 to 6

DMAIW[2:0]

000

R/W

Wait states between access cycles when DMA single

address transfer is performed.

Specify the number of idle cycles to be inserted after

an access to an external device with DACK when DMA

single address transfer is performed. The method of

inserting idle cycles depends on the contents of

DMAIWA.

000: No idle cycle inserted

001: 1 idle cycle inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

100: 6 idle cycles inserted

101: 8 idle cycles inserted

110: 10 idle cycles inserted

111: 12 idle cycles inserted

DMAIWA

R/W

Method of inserting wait states between access cycles

when DMA single address transfer is performed.

Specifies the method of inserting the idle cycles

specified by the DMAIW[2:0] bit. Clearing this bit will

make this LSI insert the idle cycles when another

device, which includes this LSI, drives the data bus

after an external device with DACK drove it. However,

when the external device with DACK drives the data

bus continuously, idle cycles are not inserted. Setting

this bit will make this LSI insert the idle cycles after an

access to an external device with DACK, even when

the continuous access cycles to an external device

with DACK are performed.

0: Idle cycles inserted when another device drives the

data bus after an external device with DACK drove

it.

1: Idle cycles always inserted after an access to an

external device with DACK



Reserved

This bit is always read as 1. The write value should

always be 1.

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