SH7243 datasheet(289/1726 Pages) RENESAS

289 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 259 of 1692

REJ09B0393-0100

9.4.2

CSn Space Bus Control Register (CSnBCR) (n = 0 to 7)

CSnBCR is a 32-bit readable/writable register that specifies the type of memory connected to a

space, data bus width of an area, endian, and the number of waits between access cycles. This

and in software standby mode.

Do not access external memory other than area 0 until CSnBCR initial setting is completed.

Idle cycles may be inserted even when they are not specified. For details, see section 9.5.10, Wait

between Access Cycles.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

0011011011011011

R/W

00000

000000000

R/W

IWW[2:0]

IWRWD[2:0]

IWRWS[2:0]

IWRRD[2:0]

IWRRS[2:0]

TYPE[2:0]

ENDIAN

BSZ[1:0]

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

30 to 28

IWW[2:0]

011

R/W

Idle Cycles between Write-Read Cycles and Write-

Write Cycles

These bits specify the number of idle cycles to be

inserted after the access to a memory that is

connected to the space. The target access cycles are

the write-read cycle and write-write cycle.

000: No idle cycle inserted

001: 1 idle cycle inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

100: 6 idle cycles inserted

101: 8 idle cycles inserted

110: 10 idle cycles inserted

111: 12 idle cycles inserted

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