SH7243 datasheet(278/1726 Pages) RENESAS

278 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 248 of 1692

REJ09B0393-0100

9.2

Input/Output Pins

Table 9.1 shows the pin configuration of the BSC.

Table 9.1

Pin Configuration

Name

I/O

Function

A25 to A0

Output

Address bus (A20 to A0 in SH7285 and SH7243)

D31 to D0

I/O

Data bus (D15 to D0 in SH7285 and SH7243)

Output

Bus cycle start

CS0 to CS7

Output

Chip select

RD/

Output

Read/write

Connects to

WE pins when SDRAM or SRAM with byte selection is

connected.

Output

Read pulse signal (read data output enable signal)

Functions as a strobe signal for indicating memory read cycles when

PCMCIA is used.

Output

A signal used to hold an address when MPX-I/O is in use

WRHH/DQMUU Output

Indicates that D31 to D24 are being written to (only in SH7286).

Connected to the byte select signal when SRAM with byte selection is

connected.

Functions as the select signals for D31 to D24 when SDRAM is

connected.

WRHL/DQMUL

Output

Indicates that D23 to D26 are being written to (only in SH7286).

Connected to the byte select signal when SRAM with byte selection is

connected.

Functions as the select signals for D23 to D26 when SDRAM is

connected.

WRH/DQMLU

Output

Indicates that D15 to D8 are being written to.

Connected to the byte select signal when a SRAM with byte selection

is connected.

Functions as the select signals for D15 to D8 when SDRAM is

connected.

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