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SH7243 Datasheet(PDF) 277 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 277 Page - Renesas Technology Corp |
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277 / 1726 page  Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 247 of 1692 REJ09B0393-0100 CMNCR CS0WCR CS7WCR CS0BCR CS7BCR SDCR RTCSR RTCNT RTCOR Comparator Bus mastership controller Wait controller Area controller Memory controller Refresh controller [Legend] BSC CS0 to CS7 REFOUT WAIT MD1, MD0 A25 to A0*, D31 to D0* BACK BREQ BS, RD/WR, RD, WRx, RASL, RASU*, CASL, CASU*, CKE, DQMxx, AH, CMNCR: CSnWCR: CSnBCR: SDCR: RTCSR: RTCNT: RTCOR: Common control register CSn space wait control register (n = 0 to 7) CSn space bus control register (n = 0 to 7) SDRAM control register Refresh timer control/status register Refresh timer counter Refresh time constant register Note * A20 to A0, D15 to D0, RASL, and CASL are available only in the SH7285 and the SH7243. Figure 9.1 Block Diagram of BSC |
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