M30201 datasheet(22/415 Pages) RENESAS

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Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Memory

Operation of Functional Blocks

The M30201 accommodates certain units in a single chip. These units include ROM and RAM to store

instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also

included are peripheral units such as timers, serial I/O, A-D converter, and I/O ports.

The following explains each unit.

Memory

Figure 1.6 is a memory map of the M30201. The address space extends the 1M bytes from address

0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30201M4-XXXSP, there is 32K

bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as the reset are

mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address

of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the

section on interrupts for details.

From 0040016 up is RAM. For example, in the M30201M4-XXXSP, there is 1K byte of internal RAM from

0040016 to 007FF16. In addition to storing data, the RAM also stores the stack used when calling subrou-

tines and when interrupts are generated.

The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-

eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not

occupied is reserved and cannot be used for other purposes.

The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines

or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions

can be used as 2-byte instructions, reducing the number of program steps.

Figure 1.6. Memory map

0000016

YYYYY16

FFFFF16

0040016

XXXXX16

Internal ROM area

SFR area

For details, see

Figures 1.7 to 1.8

Internal RAM area

FFE0016

FFFDC16

FFFFF16

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer

Reset

Special page

vector table

DBC

Address

YYYYY16

007FF16

1K bytes

RAM size

00BFF16

Address

XXXXX16

F800016

32K bytes

ROM size

F400016

48K bytes

2K bytes

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