3825 datasheet(13/339 Pages) RENESAS

13 / 339 page

3825 GROUP USER’S MANUAL

List of figures

Fig. 2.6.1 Changes in A-D conversion register and comparison voltage during A-D conversion .. 2-143

Fig. 2.6.2 A-D converter equivalent connection diagram ............................................................... 2-144

Fig. 2.6.3 Memory allocation of A-D converter-related registers ................................................... 2-146

Fig. 2.6.4 Structure of A-D control register .................................................................................... 2-147

Fig. 2.6.5 Structure of A-D conversion register ............................................................................. 2-148

Fig. 2.6.6 Structure of CPU mode register .................................................................................... 2-149

Fig. 2.6.7 Structure of port P5 direction register ............................................................................ 2-150

Fig. 2.6.8 Structure of port P6 direction register ............................................................................ 2-151

Fig. 2.6.9 Structure of interrupt request register 2 ......................................................................... 2-152

Fig. 2.6.10 Structure of interrupt control register 2 ........................................................................ 2-153

Fig. 2.6.11 Absolute accuracy of A-D converter ............................................................................ 2-154

Fig. 2.6.12 Differential non-linearity error of A-D converter ........................................................... 2-155

Fig. 2.6.13 Operating conditions for using A-D converter .............................................................. 2-156

Fig. 2.6.14 Register initialization example when internal trigger is selected (1) ............................ 2-157

Fig. 2.6.15 Register initialization example when internal trigger is selected (2) ............................ 2-158

Fig. 2.6.16 Register initialization example when external trigger is selected (1) ........................... 2-159

Fig. 2.6.17 Register initialization example when external trigger is selected (2) ........................... 2-160

Fig. 2.6.18 Example of peripheral circuit ....................................................................................... 2-161

Fig. 2.6.19 Setting of related registers ........................................................................................... 2-161

Fig. 2.6.20 Control procedure ........................................................................................................ 2-162

Fig. 2.7.1 Memory allocation of LCD display-related registers ...................................................... 2-168

Fig. 2.7.2 Structure of segment output enable register ................................................................. 2-169

Fig. 2.7.3 Structure of LCD mode register ..................................................................................... 2-171

Fig. 2.7.4 Structure of port P0 direction register ............................................................................ 2-172

Fig. 2.7.5 Structure of PULL register A .......................................................................................... 2-173

Fig. 2.7.6 Example of setting registers for LCD display (1) ........................................................... 2-174

Fig. 2.7.7 Example of setting registers for LCD display (2) ........................................................... 2-175

Fig. 2.7.8 8-segment LCD panel display pattern example when the duty ratio number is 4 ......... 2-176

Fig. 2.7.9 LCD panel example ....................................................................................................... 2-177

Fig. 2.7.10 Segment allocation example ....................................................................................... 2-177

Fig. 2.7.11 LCD display RAM setting example .............................................................................. 2-177

Fig. 2.7.12 Setting of related registers ........................................................................................... 2-178

Fig. 2.7.13 Control procedure ........................................................................................................ 2-179

Fig. 2.8.1 Oscillation stabilizing time at restoration by reset input ................................................. 2-182

Fig. 2.8.2 Execution sequence example at restoration by occurrence of INT0 interrupt request .. 2-184

Fig. 2.8.3 Reset input time ............................................................................................................. 2-187

Fig. 2.8.4 State transitions of internal clock

φ......................................................................................... 2-189

Fig. 2.9.1 Internal reset state hold/release timing .......................................................................... 2-190

Fig. 2.9.2 Internal processing sequence immediately after reset release ..................................... 2-191

Fig. 2.9.3 Internal state of microcomputer immediately after reset release ................................... 2-192

Fig. 2.9.4 Poweron reset conditions .............................................................................................. 2-193

Fig. 2.9.5 Poweron reset circuit examples ..................................................................................... 2-193

Fig. 2.10.1 Oscillation circuit example using ceramic resonators .................................................. 2-195

Fig. 2.10.2 External clock input circuit example ............................................................................ 2-196

Fig. 2.10.3 Clock generating circuit block diagram ........................................................................ 2-197

Fig. 2.10.4 Structure of clock output control register ..................................................................... 2-198

Fig. 2.10.5 State transitions of internal clock

φ ...................................................................................... 2-201

Fig. 2.10.6 Oscillation stabilizing time at poweron ......................................................................... 2-202

Fig. 2.10.7 Oscillation stabilizing time at reoscillation of XIN ....................................................................... 2-203

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