3825 datasheet(29/339 Pages) RENESAS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

3825 Group

1-13

I/O PORTS

Direction Registers

The 3825 group has 43 programmable I/O pins arranged in seven

I/O ports (ports P16, P17 P2, P4–P6, P71–P77 and P8). The I/O

ports have direction registers which determine the input/output di-

rection of each individual pin. (Ports P16 and P17 are shared with

bits 6 and 7 of the port P1 output control register). Each bit in a di-

rection register corresponds to one pin, each pin can be set to be

input port or output port.

When “0” is written to the bit corresponding to a pin, that pin be-

comes an input pin. When “1” is written to that bit, that pin be-

comes an output pin.

If data is read from a pin set to output, the value of the port output

latch is read, not the value of the pin itself. Pins set to input are

floating. If a pin set to input is written to, only the port output latch

is written to and the pin remains floating.

Port P1 Output Control Register

Bit 0 of the port P1 output control register (address 000316) en-

ables control of the output of ports P10 to P15.

When the bit is set to “1”, the port output function is valid.

In this case, setting of the PULL register A to ports P10 to P15 is

invalid.

When resetting, bit 0 of the port P1 output control register is set to

“0” (the port output function is invalid.)

Pull-up/Pull-down Control

By setting the PULL register A (address 001616) or the PULL reg-

ister B (address 001716), ports P0 to P8 can control either pull-

down or pull-up (pins that are shared with the segment output pins

for LCD are pull-down; all other pins are pull-up) with a program.

However, the contents of PULL register A and PULL register B do

not affect ports programmed as the output ports. (except for ports

P0 and P3).

Ports P0 and P3 share the port output control function with bit 0 of

the PULL register A. When set to “1”, the port output function is in-

valid (Pull-down is valid).

When set to “0”, the port output function is valid (Pull-down is in-

valid).

The PULL register A setting is invalid for pins set to segment out-

put on the segment output enable register.

Fig. 10 Structure of PULL register A and PULL register B

P0, P10–P15, P3 pull-down

(shared with P0 and P3 output

control : refer to the text)

P16–P17 pull-up

P20–P27 pull-up

P80, P81 pull-up

P40–P43 pull-up

P44–P47 pull-up

Not used (return “0” when read)

PULL register A

(PULLA : address 001616)

P50–P53 pull-up

P54–P57 pull-up

P60–P63 pull-up

P64–P67 pull-up

P71–P73 pull-up

P74–P77 pull-up

Not used (return “0” when read)

0 : Disable

1 : Enable

PULL register B

(PULLB : address 001716)

Note : The contents of PULL register A and PULL register B

do not affect ports programmed as the output port.

3825 Datasheet(PDF) 29 Page - Renesas Technology Corp

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