38B7 datasheet(39/415 Pages) RENESAS

39 / 415 page

HARDWARE

1-16

38B7 Group User’s Manual

Table 6 List of I/O port functions (1)

P00/FLD8–

P07/FLD15

Nama

Port P0

Input/Output

Output

I/O Format

High-breakdown voltage

P-channel open-drain

output with pull-down

resistor

Low-voltage input level

High-breakdown voltage

P-channel open-drain

output with pull-down

resistor

High-breakdown voltage

P-channel open-drain

output with pull-down

resistor

Low-voltage input level

High-breakdown voltage

P-channel open-drain

output with pull-down

resistor

Low-voltage input level

High-breakdown voltage

P-channel open-drain

output

Low-voltage input level

High-breakdown voltage

P-channel open-drain

output

Low-voltage input level

High-breakdown voltage

P-channel open-drain

output

Low-voltage input level

(port input)

CMOS compatible input

level (RxD, SCLK21,

SCLK22)

CMOS 3-state output

Non-Port Function

FLD automatic display

function

Related SFRs

FLDC mode register

P0 digit output set switch

Ref.No.

(1)

(2)

FLDC mode register

FLD automatic display

function

Serial I/O2 function I/O

P10/FLD16–

P17/FLD23

Port P1

Input/output,

individual

bits

FLDC mode register

P2 digit output set switch

(1)

P20/FLD0–

P27/FLD7

Port P2

Output

P30/FLD24–

P37/FLD31

Port P3

Input/output,

individual

bits

FLDC mode register

(2)

FLDC mode register

Port P4 FLD/Port switch

(2)

P40/FLD32–

P47/FLD39

Port P4

Input/output,

individual

bits

Input/output,

individual

bits

P50/FLD40–

P57/FLD47

Port P5

FLDC mode register

Port P5 FLD/Port switch

(2)

FLDC mode register

Port P6 FLD/Port switch

(2)

Input/output,

individual

bits

Port P6

P60/FLD48–

P63/FLD51

P64/RxD/

FLD52

P65/TxD/

FLD53,

P66/SCLK21/

FLD54

P67/SRDY2/

SCLK22/

FLD55

P70/INT0,

P71/INT1

P72/INT2

CMOS compatible input

level

CMOS 3-state output

FLDC mode register

Serial I/O2 control

UART control register

Interrupt edge selection

(3)

(4)

(5)

(6)

Port P7

Input/output,

individual

bits

External interrput input

Interrupt edge selection

Interrupt interval determi-

nation control register

Interrupt edge selection

FLD output control register

Timer 56 mode register

Timer 12 mode register

Timer 34 mode register

Buzzer output control

Interrupt edge selection

CPU mode register

(7)

P73/INT3/

DIMOUT

External interrput input

Dimmer signal output

(8)

P74/PWM1

P75/T1OUT

P76/T3OUT

P77/INT4/

BUZ01

CMOS compatible input

level

CMOS 3-state output

PWM output

Timer output

Buzzer output

External interrput input

(9)

Sub-clock generating

circuit I/O

External count input

P80/XCIN

P81/XCOUT

P82/CNTR1

P83/CNTR0/

CNTR2

Port P8

Input/output,

individual

bits

(10)

(11)

(6)

(12)

Interrupt edge selection

FUNCTIONAL DESCRIPTION

38B7 Datasheet(PDF) 39 Page - Renesas Technology Corp

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