38B7 datasheet(15/415 Pages) RENESAS

15 / 415 page

38B7 Group User’s Manual

List of figures

Fig. 2.3.1 Memory map of registers relevant to Serial I/O .................................................... 2-37

Fig. 2.3.2 Structure of Serial I/O1 automatic transfer data pointer ...................................... 2-38

Fig. 2.3.3 Structure of Serial I/O1 control register 1 .............................................................. 2-39

Fig. 2.3.4 Structure of Serial I/O1 control register 2 .............................................................. 2-40

Fig. 2.3.5 Structure of Serial I/O1 register/Transfer counter ................................................. 2-41

Fig. 2.3.6 Structure of Serial I/O1 control register 3 .............................................................. 2-42

Fig. 2.3.7 Structure of Baud rate generator ............................................................................. 2-43

Fig. 2.3.8 Structure of UART control register .......................................................................... 2-43

Fig. 2.3.9 Structure of Serial I/O2 control register .................................................................. 2-44

Fig. 2.3.10 Structure of Serial I/O2 status register ................................................................. 2-45

Fig. 2.3.11 Structure of Serial I/O2 transmit/receive buffer register ..................................... 2-45

Fig. 2.3.12 Structure of Serial I/O3 control register ................................................................ 2-46

Fig. 2.3.13 Structure of Serial I/O3 register ............................................................................. 2-46

Fig. 2.3.14 Structure of Interrupt source switch register ........................................................ 2-47

Fig. 2.3.15 Structure of Interrupt request register 1 ............................................................... 2-47

Fig. 2.3.16 Structure of Interrupt request register 2 ............................................................... 2-48

Fig. 2.3.17 Structure of Interrupt control register 1 ................................................................ 2-49

Fig. 2.3.18 Structure of Interrupt control register 2 ................................................................ 2-49

Fig. 2.3.19 Serial I/O1 connection examples (1) ..................................................................... 2-50

Fig. 2.3.20 Serial I/O1 connection examples (2) ..................................................................... 2-51

Fig. 2.3.21 Serial I/O1’s modes ................................................................................................. 2-52

Fig. 2.3.22 Connection diagram ................................................................................................. 2-53

Fig. 2.3.23 Timing chart .............................................................................................................. 2-53

Fig. 2.3.24 Registers setting relevant to transmission side ................................................... 2-54

Fig. 2.3.25 Setting of transmission data ................................................................................... 2-54

Fig. 2.3.26 Control procedure ..................................................................................................... 2-55

Fig. 2.3.27 Connection diagram ................................................................................................. 2-56

Fig. 2.3.28 Timing chart of serial data transmission/reception .............................................. 2-56

Fig. 2.3.29 Relevant registers setting ....................................................................................... 2-57

Fig. 2.3.30 Control procedure ..................................................................................................... 2-58

Fig. 2.3.31 Serial I/O2 connection examples (1) ..................................................................... 2-59

Fig. 2.3.32 Serial I/O2 connection examples (2) ..................................................................... 2-60

Fig. 2.3.33 Serial I/O2’s modes ................................................................................................. 2-61

Fig. 2.3.34 Serial I/O2 transfer data format ............................................................................. 2-61

Fig. 2.3.35 Connection diagram ................................................................................................. 2-62

Fig. 2.3.36 Timing chart .............................................................................................................. 2-62

Fig. 2.3.37 Registers setting relevant to transmission side ................................................... 2-63

Fig. 2.3.38 Registers setting relevant to reception side ......................................................... 2-64

Fig. 2.3.39 Control procedure of transmission side ................................................................ 2-65

Fig. 2.3.40 Control procedure of reception side ...................................................................... 2-66

Fig. 2.3.41 Connection diagram ................................................................................................. 2-67

Fig. 2.3.42 Timing chart .............................................................................................................. 2-67

Fig. 2.3.43 Relevant registers setting ....................................................................................... 2-68

Fig. 2.3.44 Setting of transmission data ................................................................................... 2-68

Fig. 2.3.45 Control procedure ..................................................................................................... 2-69

Fig. 2.3.46 Connection diagram ................................................................................................. 2-70

Fig. 2.3.47 Timing chart .............................................................................................................. 2-71

Fig. 2.3.48 Relevant registers setting in master unit .............................................................. 2-71

Fig. 2.3.49 Relevant registers setting in slave unit ................................................................ 2-72

Fig. 2.3.50 Control procedure of master unit ........................................................................... 2-73

Fig. 2.3.51 Control procedure of slave unit ............................................................................. 2-74

Fig. 2.3.52 Connection diagram ................................................................................................. 2-75

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