38B7 datasheet(59/415 Pages) RENESAS

59 / 415 page

HARDWARE

1-36

38B7 Group User’s Manual

FUNCTIONAL DESCRIPTION

4. SRDY1 output signal

The SRDY1 output is a transmit/receive enable signal which in-

forms the serial transfer destination that transmit/receive is ready.

In the initial status, when the serial I/O initialization bit (b4) is reset

to “0”, the SRDY1 output goes to “L” and the SRDY1 output goes to

“H”. After transmitted data is stored in the serial I/O1 register (ad-

dress 001B16) and a transmit/receive operation becomes ready,

the SRDY1 output goes to “H” and the SRDY1 output goes to “L”.

When a transmit/receive operation is started and the transfer clock

goes to “L”, the SRDY1 output goes to “L” and the SRDY1 output

goes to “H”.

5. SRDY1 input signal

The SRDY1 input signal becomes valid only when the SRDY1 input

and the SBUSY1 output are used. The SRDY1 input is a signal for

receiving a transmit/receive ready completion signal from the se-

rial transfer destination.

When the internal synchronous clock is selected, input a low level

signal into the SRDY1 input and a high level signal into the SRDY1

input in the initial status in which the transfer is stopped.

When an “H” level signal is input into the SRDY1 input and an “L”

level signal is input into the SRDY1 input for a period of 1.5 cycles

or more of transfer clock, transfer clocks are output from the

SCLK1 output and a transmit/receive operation is started.

After the transmit/receive operation is started and an “L” level sig-

nal is input into the SRDY1 input and an “H” level signal into the

SRDY1 input, this operation cannot be immediately stopped.

After the specified number of bits are transmitted and received,

the transfer clocks from the SCLK1 output is stopped. The hand-

shake unit of the 8-bit serial I/O and that of the automatic transfer

serial I/O are of 8 bits.

When the external synchronous clock is selected, the SRDY1 input

becomes one of the triggers to output the SBUSY1 signal.

To start a transmit/receive operation (SBUSY1 output: “L”, SBUSY1

output: “H”), input an “H” level signal into the SRDY1 input and an

“L” level signal into the SRDY1 input, and also write transmit data

into the serial I/O1 register.

Fig. 32 SRDY1 output operation

Fig. 33 SRDY1 input operation (internal synchronous clock)

SRDY1

SCLK1

Write to serial

I/O1 register

SRDY1

SCLK1

SOUT1

38B7 Datasheet(PDF) 59 Page - Renesas Technology Corp

38B7 Datasheet(HTML) 59 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL