38B7 datasheet(13/415 Pages) RENESAS

13 / 415 page

38B7 Group User’s Manual

List of figures

Fig. 47 Structure of FLDC related registers (3) ...................................................................... 1-48

Fig. 48 Structure of FLDC related registers (4) ...................................................................... 1-49

Fig. 49 Segment/Digit setting example ..................................................................................... 1-50

Fig. 50 FLD automatic display RAM assignment .................................................................... 1-51

Fig. 51 Example of using FLD automatic display RAM in 16-timing•ordinary mode ......... 1-52

Fig. 52 Example of using FLD automatic display RAM in 16-timing•gradation display mode

........................................................................................................................................................ 1-53

Fig. 53 Example of using FLD automatic display RAM in 32-timing mode ......................... 1-54

Fig. 54 FLD and digit output timing .......................................................................................... 1-55

Fig. 55 Timing using digit interrupt ........................................................................................... 1-56

Fig. 56 Timing using FLD blanking interrupt ............................................................................ 1-57

Fig. 57 P64 to P67 FLD output pulses ...................................................................................... 1-58

Fig. 58 Toff section generating/nothing function ..................................................................... 1-59

Fig. 59 Digit pulses output function .......................................................................................... 1-60

Fig. 60 Structure of AD/DA control register ............................................................................. 1-61

Fig. 61 Black diagram of A-D converter ................................................................................... 1-61

Fig. 62 Black diagram of D-A converter ................................................................................... 1-62

Fig. 63 Equivalent connection circuit of D-A converter .......................................................... 1-62

Fig. 64 PWM block diagram ....................................................................................................... 1-63

Fig. 65 PWM timing ..................................................................................................................... 1-64

Fig. 66 Structure of PWM control register ............................................................................... 1-65

Fig. 67 14-bit PWM timing .......................................................................................................... 1-65

Fig. 68 Interrupt interval determination circuit block diagram ............................................... 1-66

Fig. 69 Structure of itnerrupt interval determination control register .................................... 1-67

Fig. 70 Interrupt inteval determination operation example (at rising edge active) ............. 1-67

Fig. 71 Interrupt interval determination operation example (at both-sided edge active) ... 1-67

Fig. 72 Block diagram of watchdog timer ................................................................................. 1-68

Fig. 73 Structure of watchdog timer control register .............................................................. 1-68

Fig. 74 Block diagram of buzzer output circuit ........................................................................ 1-69

Fig. 75 Structure of buzzer output control register ................................................................ 1-69

Fig. 76 Reset circuit example .................................................................................................... 1-70

Fig. 77 Reset sequence .............................................................................................................. 1-70

Fig. 78 Internal status at reset .................................................................................................. 1-71

Fig. 79 Ceramic resonator circuit .............................................................................................. 1-72

Fig. 80 External clock input circuit ............................................................................................ 1-72

Fig. 81 Clock generating circuit block diagram ....................................................................... 1-73

Fig. 82 State transitions of system clock ................................................................................. 1-74

Fig. 83 Digit timing waveform (1) .............................................................................................. 1-76

Fig. 84 Digit timing waveform (2) .............................................................................................. 1-77

Fig. 85 Pin connection of M38B79FF when operating in parallel input/output mode ........ 1-80

Fig. 86 Read timong .................................................................................................................... 1-81

Fig. 87 Timings during reading .................................................................................................. 1-82

Fig. 88 Input/output timings during programming (Verify data is output at the same timing as

for read.) ......................................................................................................................... 1-83

Fig. 89 Input/output timings during erasing (verify data is output at the same timing as for

read.) ................................................................................................................................1-84

Fig. 90 Programming/Erasing algorithm flow chart ................................................................. 1-86

Fig. 91 Pin connection of M38B79FF when operating in serial I/O mode .......................... 1-88

Fig. 92 Timings during reading .................................................................................................. 1-90

Fig. 93 Timings during programming ......................................................................................... 1-91

Fig. 94 Timings during program verify ...................................................................................... 1-91

Fig. 95 Timings at erasing .......................................................................................................... 1-92

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