7733 datasheet(343/940 Pages) RENESAS

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CONNECTING EXTERNAL DEVICES

7733 Group User’s Manual

12–18

<<No wait>>

Sampling timing

Clock

CPU

RDY

ALE

Bus is not in use.

Bus is in use.

Ready state is terminated.

“L” level which is input to pin RDY is

accepted, so that signal E is stopped

at “H” level for 1 cycle of clock

(area

), and

CPU

is stopped

at “L” level.

“L” level which is input to pin RDY

is not accepted, but

CPU

is stopped at

“L” level.

“L” level which is input to pin RDY

is accepted, so that signal E is stopped

at “L” level for 1 cycle of clock

(area

), and

CPU

is stopped at

“L” level.

“L” level which is input to pin RDY is not

accepted because it is sampled

immediately before a wait generated by

software (area

), but

CPU

is stopped

at “L” level.

Sampling timing

Clock

CPU

RDY

ALE

<<Wait 0>>

Bus is in use.

Sampling timing

Clock

CPU

RDY

ALE

<<Wait 1>>

Bus is in use.

Fig. 12.3.1 Timings when ready state is accepted and terminated

12.3 Ready function

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