7733 datasheet(345/940 Pages) RENESAS

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CONNECTING EXTERNAL DEVICES

7733 Group User’s Manual

12–20

12.4.1 Operation in Hold state

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When “L” level is input to pin HOLD while the bus is not in use, this signal is accepted at the falling edge

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of clock

φ1 in each bus cycle. When “L” level is input to pin HOLD while the bus is in use, this signal is

accepted at the last falling edge of clock

φ1. (Refer to Figures 12.4.2 to 12.4.6.) When word data which

starts from an odd address is accessed by the two bus cycles, determination is performed only in the

second bus cycle. (Refer to Figure 12.4.1.)

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When “L” level which was input to pin HOLD is accepted,

φCPU is stopped at the next rising edge of clock

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φ1. At this time, pin HLDA outputs “L” level, and so the external is informed that the microcomputer is in

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____

the hold state. After one cycle of clock

φ1 has passed since pin HLDA’s level becomes “L,” pins R/W, BHE

and the external bus enter the floating state.

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The hold state can be terminated by setting pin HOLD’s level to “H” again. When “H” level is input to pin

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HOLD

, the signal is accepted at the falling edge of clock

φ1. When “H” level which was input to pin HOLD

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is accepted, pin HLDA’s level goes from “L” to “H.” And then, the hold state is terminated after one cycle

of clock

φ1 has passed.

Figures 12.4.2 to 12.4.6 show the timing when the hold state is accepted and terminated.

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g In the ready state, determination of pin HOLD’s input level is not performed.

Clock

ALE

At reading

At writing

q Determination timing of pin HOLD’s input level

Not

determined

Determined

Word data is accessed by the two bus cycles.

(in this case, no wait)

Fig.12.4.1 Determination when word data which starts from odd address is accessed by the two bus

cycles

12.4 Hold function

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