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7733 Datasheet(PDF) 350 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 350 Page - Renesas Technology Corp |
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350 / 940 page  CONNECTING EXTERNAL DEVICES 7733 Group User’s Manual 12–25 When “L” level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. Sampling is not performed until 16-bit data input/output is finished. ( “L” level input to pin HOLD is not accepted.) External address bus/ External data bus ALE E HLDA HOLD R/W Address 1 ! 1 1 ! 1 Hold state Not sampled External data bus Data length External data bus width Software wait 16 8 16 (When accessed starting from odd address) No wait In use q State when “L” level is input to pin HOLD Sampling timing Bus is in use. <<When “L” level is input to pin HOLD while bus is in use (4)>> External address bus Clock 1 Data High-order address Floating Floating Floating Bus is in use. BHE Data Low-order address 12.4 Hold function Fig. 12.4.6 Timing when hold state is accepted and terminated (5) |
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