7733 datasheet(385/940 Pages) RENESAS

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ELECTRICAL CHARACTERISTICS

7733 Group User’s Manual

15–6

Limits

320

160

Limits

15.5 Internal peripheral devices

Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless

otherwise noted)

g The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted.

15.5 Internal peripheral devices

tc(TA)

tw(TAH)

tw(TAL)

TAiIN input cycle time

TAiIN input high-level pulse width

TAiIN input low-level pulse width

Min.

Max.

Unit

Symbol

Parameter

tc(TA)

tw(TAH)

tw(TAL)

TAiIN input cycle time (Note 3)

TAiIN input high-level pulse width (Note 3)

TAiIN input low-level pulse width (Note 3)

Min.

Max.

Unit

Symbol

Parameter

Timer A input (Gating input in timer mode)

Parameter

Limits

Timer A input (External trigger input in one-shot pulse mode)

TAiIN input cycle time

TAiIN input high-level pulse width

TAiIN input low-level pulse width

Max.

Unit

Symbol

Min.

320

tc(TA)

tw(TAH)

tw(TAL)

Limits

TAiIN input high-level pulse width

TAiIN input low-level pulse width

Min.

Max.

tw(TAH)

tw(TAL)

Unit

Parameter

Symbol

tc(UP)

tw(UPH)

tw(UPL)

tsu(UP–TIN)

th(TIN–UP)

TAiOUT input cycle time

TAiOUT input high-level pulse width

TAiOUT input low-level pulse width

TAiOUT input setup time

TAiOUT input hold time

Min.

Max.

Unit

Symbol

Parameter

Timer A input (Up-down input in event counter mode)

Timer A input (External trigger input in pulse width modulation mode)

2000

1000

400

Timer A input (Count input in event counter mode)

Data formula (Min.)

8 ! 109

f(f2)

4 ! 109

f(f2)

4 ! 109

f(f2)

(Note 2)

8 ! 109

f(f2)

(Note 2)

Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.

2: f(f2) represents the clock f2 frequency.

For the relationship with the main clock and sub clock, refer to Table 14.3.1.

3: The TAiIN input cycle time must be 4 cycles of a count source or more.

The TAiIN input high-level pulse width and low-level pulse width must be 2 cycles of a count source

or more, respectively.

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