7733 datasheet(457/940 Pages) RENESAS

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7733 Group User’s Manual

17–50

(2) Initial settings for related registers

Fig. 17.4.4 Initial settings for related registers

X: It may be “0” or “1.”

Timer B2 interrupt control register (address 7C 16)

Interrupt priority level is set. (Note that a value other than “000 2” is set.)

Interrupt request bit: 0 (Initialized)

Interrupt disable flag (I)

“0”: Interrupt is enabled.

INT0

interrupt control register (address 7D 16)

Interrupt priority level is set. (Note that a value other than “000 2” is set.)

Interrupt request bit: 0 (Initialized)

An interrupt request occurs at the falling edge.

Interval of the clock timer’s interrupt request

occurrence: 1 second

b15

Timer B2 register (addresses 55 16 and 5416)

0316

FF16

Settings for the clock timer

Timer B2 mode register (address 5D 16)

0 1

XCIN-XCOUT is selected. (Sub clock is used.)

Oscillation circuit control register 0 (address 6C 16)

In the wait mode, clocks

512

are stopped.

An external clock is selected as the main clock.

Watchdog timer is not used when the stop mode is terminated.

Oscillation circuit control register 1 (address 6F 16)

X1 1 1

An external clock is selected as the sub clock and P7 6 functions as a port.

Watchdog timer is not used when the stop mode is terminated.

In the one time PROM version or EPROM version of the 7733 Group, this bit

must be fixed to “1.” (In 7735 Group, this bit must be fixed to “0.” )

Must be fixed to “0.”

Note: When writing a value to this register, write a value of “55 16” by executing the LDM instruction,

and then write a desired value. (Refer to Figure 11.2.4. )

17.4 Power saving

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