7733 datasheet(458/940 Pages) RENESAS

458 / 940 page

APPLICATIONS

7733 Group User’s Manual

17–51

(3) Approximate flowchart

Fig. 17.4.5 Approximate flowchart (1)

[F_WIT]: Flag used to determine whether an INT0 interrupt

request has occurred or not

Main clock oscillation circuit: Oscillating

<<C>>

Main routine

System clock selection bit

“1”

(bit 3 at address 6C 16)

System clock:

Main clock

Sub clock

<<A>>

VREF connection selection bit

“1”

(bit 5 at address 1F 16)

Pin VREF is disconnected from resistor ladder network.

(Note 1)

Port level is fixed.

(Note 2)

Wait mode is selected.

Main clock stop bit

“1”

(bit 2 at address 6C 16)

Main clock oscillation circuit: Stopped

<<B>>

Main clock stop bit

“0”

(bit 2 at address 6C 16)

0: INT0 interrupt

[F_WIT]

“1”

Clock timer

interrupt request

occurs.

[F_WIT] = “1” ?

“1”: Clock timer

interrupt

WIT

INT0

interrupt

request occurs.

(By this setting, the wait mode is terminated

only when an INT0 interrupt request occurs.)

Bits 2 to 0 at addresses 70 16

to 7B16, 7E16, and 7F16

“0002”

Interrupts other than timer B2 and INT0 interrupts are

disabled.

Timer B2 count start flag

“1”

(bit 7 at address 40 16)

Clock timer starts counting .

System clock selection bit

“0”

(bit 3 at address 6C 16)

System clock:

Sub clock

Main clock (Note 3)

<<D>>

<<A>> <<B>> <<C>> <<D>>: Refer to Figure 17.4.8.

For Notes 1 to 3, refer to the next page.

17.4 Power saving

7733 Datasheet(PDF) 458 Page - Renesas Technology Corp

7733 Datasheet(HTML) 458 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL