7733 datasheet(462/940 Pages) RENESAS

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APPLICATIONS

7733 Group User’s Manual

17–54

17.5 Timer B

An application example of the clock timer (Timer B) is described below.

17.5.1 Application example of clock timer

In this example, the clock timer is controlled by a clock of 32.768 kHz. When the main power source is

off, the clock timer can continue counting for the maximum of approximate 45 days by using the backup

power source and the internal connect function between timers B1 and B2.

(1) Specifications

Main power source = 5 V to 2.75 V. Backup power source = 2.75 V to 2.2 V

Timer B2 uses the sub clock (32.768 kHz) divided by 32 as the count source and counts the time

up to 1 minute.

Timer B2 counts the power-source-off time up to the maximum of approximate 45 days, checking

the timer B2’s overflow signal.

The clock counter is counted up each time timer B2 interrupt occurs, in other words, every 1 minute.

When Vcc is less than 2.75 V, in other words, when the main power source is off, the INT0 input’s

level changes from “H” to “L” and the microcomputer enters the wait mode at this falling edge.

(Refer to “a” in Figure 17.5.2.)

In the wait mode (Vcc = 2.2 V or more), only timers B2 and B1 do counting. (In this case, note that

clock display is disabled and the timer B2 and B1 interrupts are disabled.)

When Vcc = 2.75 V or more in the wait mode, in other words, when the main power source is on,

the INT0 input’s level changes from “L” to “H” and the wait mode is terminated at the INT0 input’s

rise. (Refer to “b” in Figure 17.5.2.) At this time, the following is done according to the timer B1’s

state.

•When no overflow has occurred in timer B1 (Timer B1 interrupt request bit = “0”), timer B1’s value

is added to the clock counter’s value which was obtained immediately before the wait mode.

•When an overflow has occurred in timer B1, in other words, when a period of approximate 45 days

or more has passed, a message for resetting time is displayed.

When Vcc = 2.2 V or less, the microcomputer enters the reset state owing to the power source

detection circuit. (Refer to “c” in Figure 17.5.2.) And then, when Vcc = 2.75 V or more, the

microcomputer is released from reset state. (Refer to “d” in Figure 17.5.2.)

Fig. 17.5.1 Connection example

Detection voltage

Vcc

RESET

INT0

Vss

XCIN

XCOUT

32.768 kHz

M37733MHBXXXFP

Power source detection circuit

Reset signal

Control signal

Clock display

Main power source (5 V)

Backup power source

17.5 Timer B

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