7733 datasheet(464/940 Pages) RENESAS

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7733 Group User’s Manual

17–56

(3) Initial settings for related registers

Fig. 17.5.4 Initial settings for related registers

b15

EFFF16

Clocks f2 to f512 are operating in the wait mode. (Note 2)

Oscillation circuit control register 0 (address 6C 16)

Sub clock is used. (Note 1)

Timer B1 mode register (address 5C 16)

Timer B2 mode register (address 5D 16)

01: Count at the rising edge

01: Event counter mode

Timer B1 interrupt control register (address 7B 16)

No interrupt is requested.

Interrupt is disabled.

Timer B2 interrupt control register (address 7C 16)

Interrupt priority level (any value other than “000 2”) is set.

No interrupt is requested.

Port function control register (address 6D 16)

Timers B1 and B2 are connected internally.

Must be fixed to “0.”

XXX

0X X

INT0 interrupt control register (address 7D 16)

Interrupt priority level (any value other than “000 2”) is set.

Edge sense

Interrupt request bit is set at the falling edge ( “H” to “L”).

No interrupt is requested.

Timer B2 register (addresses 55 16 and 5416)

b15

FFFF16

Timer B1 register (addresses 53 16 and 5216)

X: It may be “0” or “1.”

Notes 1: Once this bit is set to “1,” it cannot be cleared to “0.”

2: When setting this bit to “1,” set “1” to this bit immediately before the WIT instruction is executed.

Furthermore, clear this bit to “0” immediately after the wait mode is terminated.

17.5 Timer B

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