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7733 Datasheet(PDF) 465 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 465 Page - Renesas Technology Corp |
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465 / 940 page ![]() APPLICATIONS 7733 Group User’s Manual 17–57 (4) Approximate flowchart Fig. 17.5.5 Approximate flowchart Clock prescaler is initialized. A value of “8016” is written to address 6F 16 by executing the LDM instruction. Main routine INT0 interrupt control register “11 16” (address 7D16) Oscillation circuit control register (address 6F 16) “8016” Count start flag (address 40 16) “C016” Timer B2 interrupt routine Count-up processing for clock RTI Counted up every minute INT0 interrupt routine INT0 level/edge selection bit = “?” (bit 4 at address 7D 16) Timer B1 count start flag “0” (bit 6 at address 40 16) By setting interrupt priority level, interrupts other than INT 0 are disabled. System clock stop bit at wait state (bit 5 at address 6C 16) “1” Timer B1 count start flag “1 ” (bit 6 at address 40 16) Timer B1 register FFFF 16 (addresses 5316 and 5216) Timer B1 count start flag “0” (bit 6 at address 40 16) Timer B1 register FFFE 16 (addresses 5316 and 5216) Timer B1 count start flag “1” (bit 6 at address 40 16) Make INT0 interrupt priority level higher. WIT instruction Make INT0 interrupt priority level to the former level. RTI INT0 interrupt control register (address 7D16) “01 16” Timer B1 interrupt request bit = ? (bit 3 at address 7B 16) Count value of timers B1 and B2 Clock counter Display urging user to set time again INT0 interrupt polarity is selected. (Falling edge: “H” “L”) INT0 interrupt polarity is selected. (Rising edge: “L” “H”) Counting for timer B1 stops. Counting for timer B1 starts. Counting for timer B1 stops. 0: No request 0: No request 1: Requested 1: Rising edge (“L” “H”) 0: Falling edge (“H” “L”) Count start flag Counting for timers B1 and B2 start 1: Requested g By software initial settings, interrupt priority level is set as follows: q Timer B2 < INT0 Counting for timer B1 starts. Timer B2 interrupt request bit = ? (bit 3 at address 7C 16) 17.5 Timer B |
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